A Task-centric Memory Model for Scalable Accelerator Architectures

John Kelm, Daniel Johnson, Steven Lumetta, Matthew Frank and Sanjay Patel

This paper presents a task-centric memory model for 1000+ core single-chip multiprocessors. We use the Rigel Task Model (RTM), a task-based low-level programming interface for supporting fine-grained work distribution, to evaluate our memory model. RTM exploits the task-centric memory memory model to enable a form of bulk-synchronous processing. We demonstrate RTM in simulation on a 1024-core MIMD accelerator we are developing that implements the memory model we propose. The architecture provides minimal hardware support for global cache coherence and task management. In lieu of specialized hardware mechanisms for these features, they are enabled in software as a part of RTM. We evaluate coherence management policies related to the task-centric memory model and its impact on a common optimization, speculative hardware prefetching.

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