The Eighteenth International Conference on
Raleigh, North Carolina. September 12-16, 2009.
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Xing Zhou, Wenguang Chen and Weimin Zheng
Resource sharing can cause unfair and unpredictable performance ofconcurrently executing applications in Chip-Multiprocessors (CMP).The shared last-level cache is one of the most important sharedresources because off-chip request latency may take a significantpart of total execution cycles for data intensive applications.However, the penalty for each cache miss is not always the samebecause of Memory Level Parallelism (MLP). So fairness on cache missrate cannot guarantee performance fairness. Cache sharing managementis needed to provide performance fairness in CMP systems.This paper proposes a mechanism of cache sharing management toprovide performance fairness for concurrently executingapplications. It monitors the average MLP-aware cost of all cachemisses and uses Auxiliary Tag Directory (ATD) to dynamicallyestimate the cache misses with dedicated cache when the applicationsare actually running with shared cache. The estimated relativeslowdown for each core from dedicated environment to sharedenvironment is used to guide cache sharing in order to guaranteeperformance fairness. The experiment results show that the proposedmechanism always improves the performance fairness metric comparedto cache miss fairness policy and Pseudo LRU policy, and provideshigher throughput for most cases.