OSCAR Parallelizing Compiler Cooperative Heterogeneous Multi-core Architecture

Akihiro Hayashi, Yasutaka Wada, Hiroaki Shikano, Teruo Kamiayama, Takeshi Watanabe, Takeshi Sekiguchi and Masayoshi Mase

Department of Computer Science and Engineering, Waseda University
Tokyo, Japan

Heterogeneous multicore architectures, which integrates multiple general purpose CPU cores and special purpose accelerator cores on a chip, have become widely spread. However, heterogeneous multicores require very difficult coding for load distribution to CPU cores and accelerator cores, synchronizations and data transfer using DMA controllers. To improve product competitiveness using heterogeneous multicore, this poster proposes OSCAR parallelizing compiler cooperative heterogeneous multicore architecture. On the propsed architecture, the developed OSCAR heterogeneous multicore gives us 21.4 times speedup with four CPU cores and four accelerator cores for an MP3 audio encoder program versus sequential execution using a single CPU core. Moreover, the architecture gives us 10.0 times speedup when executing an AAC encoder program using the previous architecture. The proposed architecture, which is designed to supports OSCAR compiler, gives us good performance.

Long Abstract

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