A Hybrid Compiler-Architecture Technique to Manage Off-Chip Traffic for Multicore Chips

Bushra Ahsan
Advisor: Mohamed Zahran

City University of New York

The tremendous increase in number of cores on chip has increased traffic going on and off chip resulting in bandwidth problem. Most of the work done so far has been concentrated on reducing traffic coming on chip by improving cache performance. However, the traffic going in the other direction has received minor attention.

We aim to reduce traffic going off-chip, that is writebacks, by proposing a modified version of LRU called the Dirty Aware LRU. In DA-LRU the victim in the cache is chosen in a way to prevent a possible write. This is done by not victimizing LRU if it is dirty and looking for a possible non LRU clean block. We show in our motivational experiments why we can afford to victimize a non LRU. Thus this modification of the LRU takes into account whether a block is dirty before victimizing it. DA-LRU has different alterable versions. The number of cache blocks from which a clean block is chosen is different in each version. Based on the above technique we propose a hybrid method to use compiler support for profiling of the number of writebacks over regular intervals. We divide this number in regions and define a different version of DA-LRU in each region. A histogram is obtained through profiling which shows a view of number of writes every particular number of cycles. Based on this histogram we propose two methods to choose thresholds that define the regions.

The above compiler support technique binds writebacks between thresholds thereby making the off-chip traffic friendlier.

Long Abstract

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