Energy Efficient Synchronization Techniques For Embedded Architectures

Cesare Ferri1, and Samantha Wood23

1Brown University
2Bryn Mawr College

Advisors: Iris Bahar and Maurice Herlihy

Embedded applications in multimedia, imaging, and communications all have a high degree of exposed thread-level parallelism. However, managing concurrency is not easy, and doing so in an energy efficient manner is even harder. Recent approaches for general-purpose-systems have focused on Transactional Memory (TM) as an effective way to improve throughput but largely ignored energy implications.

In our work we target embedded systems, which are resource and energy constrained. Therefore, we focus on simple Hardware TM (HTM), which has minimal demand on resources, with the main design goal of energy efficiency.

We propose a cache-based type of HTM solution for a System-on-Chip platform technology, that was modeled with cycle-accurate precision, and with accurate power models. Beside being particularly lightweight, the architecture is also featured with: support for transactions exceeding the size of the transactional-cache(TC); ability to shutdown the TC in case of low-synchronization (to save energy); configurable setup for the degree of the TC associativity.

We are currently developing new energy-efficient strategies with the aim of improving the system throughput. For example, to reduce the likelihood of overflow, we allow the L1 cache to store the transactional data. We are also implementing an alternative type of conflicts management, in which conflicts are resolved at commit time.

Long Abstract

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