Reliability-Constrained Processor Performance Optimization via Design Parameter Selection

Lide Duan, Bin Li and Lu Peng
Louisiana State University

High-performance processors suffer from soft error vulnerability due to increased on-chip transistors density, shrinking processor feature size, lower threshold voltage, etc. A processor configuration merely optimized for high performance sometimes leads to high vulnerability to soft errors. In this paper, we propose using two predictive techniques to optimize processor performance under reliability constraints. By exploring the microarchitectural design space on the Architectural Vulnerability Factor (AVF), our first methodology is capable of generating a set of selective rules on key design parameters. Applying these rules at early design stage effectively identifies the configurations that have the smallest values of the AVF, thus enabling the optimization of different reliability metrics. Moreover, another heuristic technique is employed to identify metrics optima with a well-trained predictive model on a considerably reduced input space. This essentially enables pareto optima analysis but avoids exhaustive evaluation of the original large design space, thereby saving prediction overhead. The derived results provide computer architects with pre-silicon guidelines in designing single- and multi-core processors with both high performance and soft error reliability.

Long Abstract

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