Designing Ef´Čücient and Safe Supervised Memory Systems

Jayaram Bobba, University of Wisconsin-Madison

An increasing number of research proposals such as transactional memory, deterministic shared memory, memory typestate trackers and log-based architectures call for hardware support of semantically richer 'supervised memory' systems wherein program data is enhanced with metadata. While the proposals address a wide range of issues from safety and security to programmability and debugging, they are all built around supervised memory operations that use metadata for controlling and monitoring data accesses to memory.

Existing proposals for supervised memory make unrealistic albeit simplifying assumptions about underlying hardware. More specifically, they assume sequential consistency which is not supported by most deployed hardware systems. Hence, practical supervised memory systems would need to be built on top of relaxed memory systems.

We show that supporting supervised memory on relaxed memory systems in non-trivial. We examine implementation issues and correctness concerns in the design of such systems. We discuss low-level issues like late exceptions that arise in implementations using store buffers and propose hardware support for addressing them. To address correctness concerns, we propose TSO_data, a TSO-like relaxed memory model for supervised memory that enables the continued use of performance optimizations like store buffers for supervised memory operations.

Long Abstract

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