Program

  Saturday, Sept 12 Sunday, Sept 13 Monday, Sept 14 Tuesday, Sept 15 Wednesday, Sept 16
7:30 Breakfast Breakfast Breakfast Breakfast Breakfast
8:00
8:30 GPU PMEA WPABA MEDEA Welcome Keynote:
Frederick H. Streitz		 Modeling and Evaluation Hardware Transactional Memory
9:00 Keynote:
Pat Hanrahan
9:30 Awards
10:00 Break Break Break Break Break
10:30 GPU PMEA WPABA MEDEA Software Transactional Memory and Speculation Power and Energy Compiler Optimizations Cache Management
11:00
11:30 ACM SRC Poster Session
12:00 Lunch Lunch Lunch Lunch  
12:30
1:00
1:30 GPU PMEA PGAS PACE Best Paper Finalists Tools and Testing Innovative Hardware
2:00
2:30
3:00 Break Break Break Break
3:30 GPU PMEA PGAS PACE Accelerators Scheduling and Adaptation Novel Cache Systems
4:00
4:30  
5:00      
5:30
6:00
6:30
7:00
7:30  
8:00  
8:30
9:00
9:30  

Tutorials Workshops Paper Sessions Special Events Breaks

Saturday, September 12

7:30-8:30
Breakfast

8:30-12:00
Workshops and Tutorials

12:00-1:30
Lunch

1:30-5:00
Workshops and Tutorials

Sunday, September 13

7:30-8:30
Breakfast

8:30-12:00
Workshops and Tutorials

12:00-1:30
Lunch

1:30-5:00
Workshops and Tutorials

6:00-8:00

Opening Reception

Monday, September 14

7:30-8:30
Breakfast

8:30-9:00

Welcome

Chairs: Sally A. McKee, Martin Schulz, Bronis R. de Supinski, and Frank Mueller

9:00-10:00

Keynote: Pat Hanrahan

Why are Graphics Systems so Fast?
Chair: Sally A. McKee

10:30-11:30
Chair: Sandhya Dwarkadas

Software Transactional Memory and Speculation

Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency.
Takayuki Usui, Yannis Smaragdakis and Reimer Behrends.

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading.
Carlos Madriles, Pedro Lopez, Josep M. Codina, Enric Gibert, Fernando Latorrre, Alejandro Martinez, Raul Martinez and Antonio Gonzalez.

11:30-12:00

ACM Student Research Competition Poster Session

12:00-1:30
Lunch

1:30-3:00
Chair: Frank Mueller

Best Paper Finalists

Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors.
Abhishek Bhattacharjee and Margaret Martonosi.

Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs.
Rajkishore Barik and Vivek Sarkar.

Quantifying the Potential for Program Analysis Peripherals.
Mohit Tiwari, Shashidhar Mysore and Timothy Sherwood.

3:30-4:30
Chair: James Dehnert

Accelerators

Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor.
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel Lacassagne and Daniel Etiemble.

A Task-centric Memory Model for Scalable Accelerator Architectures.
John Kelm, Daniel Johnson, Steven Lumetta, Matthew Frank and Sanjay Patel.

5:30-6:30

ACM Student Research Competition Presentations

6:30-7:30

Poster Reception

Tuesday, September 15

7:30-8:30
Breakfast

8:30-9:30

Keynote: Frederick H. Streitz

Pushing the Limits: Scientific Computing on Extreme Platforms
Chair: Bronis R. de Supinski

9:30-10:00

Awards

10:30-12:00
Chair: Martin Schulz

Power and Energy

SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers.
Xiaorui Wang, Ming Chen, Charles Lefurgy and Tom Keller.

Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures.
Wangyuan Zhang and Tao Li.

Core-Selectability in Chip Multiprocessors.
Hashem H. Najaf-abadi, Niket K. Choudhary and Eric Rotenberg.

12:00-1:30
Lunch

1:30-3:00
Chair: Rob Fowler

Tools and Testing

Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison.
Tipp Moseley, Dirk Grunwald and Ramesh Peri.

tm_db: A Generic Debugging Library for Transactional Programs.
Yossi Lev and Maurice Herlihy.

StealthTest: Low Overhead Online Software Testing using Transactional Memory.
Jayaram Bobba, Weiwei Xiong, Luke Yen, Mark Hill and David Wood.

Chair: James Tuck

Innovative Hardware

CPROB: Checkpoint Processing with Opportunistic Minimal Recovery.
Andrew Hilton, Neeraj Eswaran and Amir Roth.

Architecture Support for Improving Bulk Memory Copying and Initialization Performance.
Xiaowei Jiang, Yan Solihin, Li Zhao and Ravishankar Iyer.

Oblivious Routing on On-Chip Bandwidth-Adaptive Networks.
Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy, Tina Wen and Srinivas Devadas.

3:30-5:00
Chair: Albert Cohen

Scheduling and Adaptation

Exploiting Parallelism with Dependence-Aware Scheduling.
Xiaotong Zhuang, Alexandre Eichenberger, Yangchun Luo, Kevin O’Brien and Kathryn O’Brien.

ITCA: Inter-Thread Conflict-Aware CPU Accounting for CMPs.
Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu and Mateo Valero.

Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures.
Amir Hormati, Yoonseo Choi, Manjunath Kudlur, Rodric Rabbah, Trevor Mudge and Scott Mahlke.

Chair: Lars Nyland

Novel Cache Systems

DDCache: Decoupled and Delegable Cache Data and Metadata.
Hemayet Hossain, Sandhya Dwarkadas and Michael C. Huang.

Zero-Value Caches: Cancelling Loads that Return Zero.
Mafijul Md Islam and Per Stenstrom.

Improving Hardware Cache Performance Through Software-Controlled Object-Level Cache Partitioning.
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, Xiaodong Zhang and P. Sadayappan.

6:30-9:30

Banquet

Wednesday, September 16

7:30-8:30
Breakfast

8:30-10:00
Chair: Ramesh Peri

Modeling and Evaluation

Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System.
Daniel Molka, Daniel Hackenberg, Robert Schöne and Matthias S. Müller.

Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling.
Basilio Fraguela, Yevgen Voronenko and Markus Puschel.

Analytical Modeling of Pipeline Parallelism.
Angeles Navarro, Rafael Asenjo, Siham Tabik and Calin Cascaval.

Chair: Xiaotong Zhuang

Hardware Transactional Memory

FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery.
Marc Lupon, Grigorios Magklis and Antonio Gonzalez.

Improving Signatures by Locality Exploitation for Transactional Memory.
Ricardo Quislant, Eladio Gutierrez and Oscar Plata.

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading.
Leo Porter, Bumyong Choi and Dean Tullsen.

10:30-12:00
Chair: Evelyn Duesterwald

Compiler Optimizations

Polyhedral-Model Guided Loop-Nest Auto-Vectorization.
Konrad Trifunovic, Ayal Zaks, Albert Cohen and Dorit Nuzman.

Data Layout Transformation for Enhancing Locality on NUCA Chip Multiprocessors.
Qingda Lu, Christophe Alias, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin and Tin-fook Ngai.

Region based Structure Layout Optimization by Selective Data Copying.
Sandya Mannarswamy, Ramaswamy Govindarajan and Rishi Surendran.

Chair: Yan Solihin

Cache Management

SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors.
Lei Jin and Sangyeun Cho.

Using Aggressor Thread Information to Improve Shared Cache Management for CMPs.
Wanli Liu and Donald Yeung.

Cache Sharing Management for Performance Fairness in Chip Multiprocessors.
Xing Zhou, Wenguang Chen and Weimin Zheng.